Flash memory device having column predecoder capable of selecting all column selection transistors and stress test method thereof

ABSTRACT

Embodiments of the invention provide a flash memory device having a column predecoder for selecting all column selection transistors during a stress test, and also provide a stress test method for the flash memory device. An embodiment&#39;s column predecoder includes a buffer unit for inputting all column selection signals, decoder units for decoding an output of the buffer unit and column addresses, and level shifters for shifting voltage levels of column selection signals coupled to gates of the column selection transistors in response to an output of the decoder units. Since a ground voltage is applied to a bitline and a high voltage is applied to all column selection signals during the stress test, the stress test time can be shortened.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority from Korean Patent ApplicationNo. 2002-79083, filed on Dec. 12, 2002, the contents of which are herebyincorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Technical Field of the Invention

[0003] This disclosure relates to a flash memory device and, moreparticularly, to a flash memory device having a column predecodercapable of selecting all column selection transistors and a stress testmethod thereof.

[0004] 2. Description of the Related Art

[0005] A flash memory device is a highly integrated information storagedevice in which write and erase operations can be done on board. A flashmemory cell includes one field effect transistor (FET) having aselection gate, a floating gate, a source, and a drain. Variation of athreshold voltage of the flash memory cell results in fluctuation of theamount of charges on a floating gate. The fluctuation is information,which is stored in the flash memory cell. A flash memory device isclassified as either a NAND flash memory device or a NOR flash memorydevice. NAND flash memory devices are used as a mass data storagedevices, and NOR flash memory devices are used as information storagedevices for processing data at a high speed.

[0006] Generally, a NOR flash memory cell has two states, i.e., aprogrammed state and an erased state. When the NOR flash memory cell isprogrammed, residual electrons are trapped on a floating gate and athreshold voltage rises. Thus, drain-source current does not flow to aselected flash memory cell. The programmed state of the flash memorycell is called a logic “0”. When the flash memory cell is erased, thereare a small number of residual electrons on the floating gate or lots ofsource-drain current flows to the flash memory cell. The erased state ofthe flash memory cell is called a logic “1”.

[0007] A typical NOR flash memory device is now described below withreference to FIG. 1.

[0008] Referring to FIG. 1, a NOR flash memory device 100 includes anaddress buffer 110, a row predecoder 120, a row decoder 130, a cellarray 140, a column predecoder 150, a column decoder 160, and a senseamplifier 170. In the cell array 140, flash memory cells (not shown) arearranged at intersections of wordlines WLi and bitlines BLi. The addressbuffer 110 receives an address signal ADDR from the outside so as toprogram or erase the flash memory cells and divides a row address RowAddfrom a column address ColAdd by means of an output of the address buffer110. The row predecoder 120 decodes the received row address RowAdd togenerate a row selection signal RowSel. The row decoder 130 enables apredetermined wordline WLi in response to the row selection signalRowSel and drives the wordline WLi to a predetermined voltage levelaccording to an operation mode of the flash memory device 100. In aprogram mode, the wordline WLi is driven to a voltage level of 10V. Inan erase mode, it is driven to a voltage level of −10V. In a read mode,it is driven to a voltage level of 4.5V.

[0009] The column predecoder 150 decodes the received column addressColAdd to generate column selection signals ColSel1[m:0] andColSel2[n:0]. The column decoder 160 selects a predetermined bitline BLiin response to the column selection signals ColSel1[m:0] andColSel2[n:0] and connects a selected bitline BLi with the senseamplifier 170 through a data line DLi. For the convenience ofdescription, 16 bitlines BLi (i=0-15) are exemplarily described. A firstcolumn selection signal ColSel1[m:0] selects four bitlines BLi and asecond column selection signal ColSel2[n:0] selects one of the selectedfour bitlines BLi to connect the selected one bitline with the data lineDLi.

[0010] The column predecoder 150 is now explained in detail withreference to FIG. 2.

[0011] Referring to FIG. 2, the column predecoder 150 inputs columnaddresses ColAdd[3:0] to selectively generate first column selectionsignals ColSel1[3:0] and second column selection signals ColSel2[3:0].The first and second column addresses ColAdd[0] and ColAdd[1] aredecoded through a decoding block 200 to drive level shifters 202, 204,206, and 208. Each of the level shifters 202, 204, 206, and 208 isstructured as shown in FIG. 3 and generates a high voltage HV of about10V as its output OUT in response to a low-level input signal IN. Fourtransistors in the column decoder 160 corresponding to the first columnselection signals ColSel1[0], ColSel1[1], ColSel1[2], and ColSel1[3],respectively, are turned on when a high voltage HV appears as the outputOUT of the level shifter 202, 204, 206, or 208, respectively. The thirdand fourth column addresses ColAdd[2] and ColAdd[3] generate secondcolumn selection signals ColSel2[0], ColSel2[1], ColSel2[2], andColSel2[3] of high voltage HV through a decoding block 210 and levelshifters 212, 214, 216, and 218. The second column selection signalsColSel2[0], ColSel2[1], ColSel2[2], and ColSel2[3] of high voltage HVselect one of the four bitlines (BLi of FIG. 1). Each bitline BLi iscoupled to one of the four transistors that are turned by an activatedfirst column selection signal ColSel1[0], ColSel1[1], ColSel1[2], orColSel1[3]. In this way the selected signal is connected with a dataline DLi.

[0012] When the flash memory device (100 of FIG. 1) is in the programmode, a voltage of 5V˜0V is applied to a bitline of a memory cellselected according to a programming type and a voltage of 0V is appliedto a bitline of an unselected memory cell. The state of the bias of atransistor MF in a first group of transistors 161 coupled to the bitlineof the unselected memory cell is now described below with reference toFIG. 4A. A high voltage of about 10V is applied to a gate by a firstcolumn selection signal ColSel1[0] that is coupled to the gate. Avoltage of 0V is applied to a source by a bitline BLO that is coupled tothe gate. Thus, a voltage of 10V is applied between the gate and thesource of the transistor MF, and a voltage of 0V is applied to the dataline DL0 of FIG. 1 that is coupled to the unselected memory cell. Thestate of the bias of a transistor MS in a second group of transistors162 (FIG. 1) is now described below with reference to FIG. 4B. A highvoltage of about 10V is applied to a gate by a second column selectionsignal ColSel2[0] that is coupled to the gate, and a voltage of 0V isapplied to a drain by the data line DL0 that is coupled to the drain.This state is maintained until the program is completed, which leads toincreased gate oxide stress of the transistors MF and MS.

[0013] Furthermore, when the flash memory device (100 of FIG. 1) is inan erase mode, a voltage of about 9V is applied to a bulk that iscoupled to a bitline. In this case, the first and second columnselection signals ColSel1[m:0] and ColSel2[n:2] have a voltage of about0V. Accordingly, a voltage of 0V is applied to the gates of the firstgroup of the transistors 161 and a coupling voltage of 9V is applied tothe sources thereof. As a result, gate oxide stress in the first groupof transistors 161 occurs.

[0014] Over time, oxide stress from repeated program and eraseoperations degrades the gate oxide layer to cause errors in atransistor. This contributes to faulty operation of a flash memorydevice. Accordingly, there is a need for a method of detecting atransistor error caused by the degradation of the gate oxide layer.

[0015] Since the first and second column selection signals ColSel1[m:0]and ColSel2[n:2] alternately apply a high voltage, it takes a long timeto screen the transistor error by applying a stress to the first andsecond groups of the transistors in the column decoder (160 of FIG. 1).

[0016] Embodiments of the invention address these and otherdisadvantages of the prior art.

SUMMARY OF THE INVENTION

[0017] Embodiments of the invention provide a flash memory device havinga column predecoder that can significantly shorten a stress test time.

[0018] Other embodiments of the invention provide a stress test methodfor a flash memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 is a block/circuit diagram illustrating a conventionalflash memory device.

[0020]FIG. 2 is a circuit diagram illustrating the column predecoder ofFIG. 1.

[0021]FIG. 3 is a circuit diagram illustrating the level shifter of FIG.2.

[0022]FIG. 4A and FIG. 4B are cross-sectional diagrams illustrating thecolumn selection transistors of FIG. 1 and where stresses occur in thosetransistors.

[0023]FIG. 5 is a block/circuit diagram illustrating a flash memorydevice according to an embodiment of the invention.

[0024]FIG. 6 is a circuit diagram illustrating the column predecoder ofFIG. 5.

DETAILED DESCRIPTION OF THE INVENTION

[0025] Referring to FIG. 5, a flash memory device 500 is substantiallysimilar to the flash memory device 100 shown in FIG. 1 except in regardsto a column predecoder 510. The column predecoder 510 selectively orentirely generates column selection signals ColSel1[m:0] andColSel2[n:0] in response to a column address ColAdd and an all columnselection signal AllColSel. The column predecoder 510 is now explainedin detail with reference to FIG. 6.

[0026] Referring to FIG. 6, the column predecoder 510 includes a bufferunit 610, decoder units 620 and 630, and level shifters 202, 204, 206,208, 212, 214, 216, and 218. These level shifters 202, 204, 206, 208,212, 214, 216, and 218 are identical to those of FIG. 3. The buffer unit610 is composed of an inverter that receives as input the all columnselection signal AllColSel. When AllColSel is activated high, an outputof the buffer unit 610 is low. The decoder units 620 and 630 combinecolumn addresses ColAdd[0], ColAdd[1], ColAdd[2], and ColAdd[3] and theoutput of the buffer unit 610. The outputs of the first and seconddecoder units 620 and 630 are used by the level shifters 202, 204, 206,208, 212, 214, 216, and 218 to generate first and second columnselection signals ColSel1[0], ColSel1[1], ColSel1[2], ColSel1[3],ColSel2[0], ColSel2[1], ColSel2[2], and ColSel2[3], respectively.

[0027] When the output of the buffer unit 610 is low, the outputs of thedecoders 620 and 630 become low, causing the level shifters 202, 204,206, 208, 212, 214, 216, and 218 to generate ColSel1[0], ColSel1[1],ColSel1[2], ColSel1[3], ColSel2[0], ColSel2[1], ColSel2[2], andColSel2[3] at the high voltage (HV). The high voltage HV is then appliedto the gates of the column selection transistors 161 and 162 in thecolumn decoder 160 of FIG. 1, thereby turning on the column selectiontransistors. Preferably, the column selection transistors 161 and 162are composed of NMOS transistors. A high voltage may be directly appliedfrom an external source that is higher than the power supply voltage,which means that a stress application test may be conducted at one timefor all the column selection transistors 161 and 162. During the stresstest, the potential of the bitlines BLi is about 0V.

[0028] When the all column selection signal AllColSel is deactivatedlow, the output of the buffer 610 is high. When the output of the buffer610 is high, the decoder units 620 and 630 operate the same way as thedecoders 200 and 210 of FIG. 2. That is, when the first column selectionsignals ColSel1[0], ColSel1[1], ColSel1[2], and ColSel1[3] are at a highvoltage level, each signal turns on four transistors among the firstgroup of the column selection transistors (161 of FIG. 5). The third andfourth column addresses ColAdd[2] and ColAdd[3] generate the secondcolumn selection signals ColSel2[0], ColSel2[1], ColSel2[2], andColSel2[3] through the decoding block 630 and the level shifters 212,214, 216, and 218. When a second column selection signal ColSel2[0],ColSel2[1], ColSel2[2], and ColSel2[3] is at the high voltage level, itactivates one of the four transistors in the second group of columnselection transistors 162. This connects the selected data line DLi to abitline BLi (see FIG. 5) that is coupled to one of the four columnselection transistors turned on by an activated first column selectionsignals ColSel1[0], ColSel1[1], ColSel1[2], and ColSel1[3].

[0029] Alternatively, the high voltage applied by the column selectionsignal may be directly applied from a variable external voltage source.

[0030] According to embodiments of the invention, a column predecodersimultaneously selects all column selection transistors to conduct astress test. Therefore, the time required for the stress test can beshortened.

[0031] Embodiments of the invention will now be described in anon-limiting way.

[0032] In accordance with an embodiment of the invention, a flash memorydevice has a column predecoder for controlling column selectiontransistors that select a predetermined bitline among a plurality ofbitlines coupled to flash memory cell. The column predecoder includes abuffer unit that has as input an all column selection signal, decoderunits for decoding an output of the buffer unit and column addresses,and level shifters for shifting the voltage levels of column selectionsignals that are coupled to gates of the column selection transistors inresponse to an output of the decoder units. During a stress test, theflash memory device responds to the all column selection signal andapplies a high voltage of 10V or higher to the gates of the transistors.Thus, the stress test is conducted for column selection transistors withbitlines at a constant voltage level, e.g., a ground voltage level.

[0033] Preferably, the buffer unit includes an inverter that receives asinput the all column selection signal. Each of the decoder unitsincludes a NAND gate for inputting an output of the buffer and thecolumn address. The level shifter includes first and second PMOStransistors, an inverter for inputting the output of the decoder unit,and first and second NMOS transistors. Sources of the first and secondPMOS transistors are coupled to a high voltage, and their gates arecross-coupled to their drains. The first NMOS transistor is coupledbetween the drain of the first PMOS transistor and a ground voltage andgates to the output of the inverter. The second NMOS transistor iscoupled between the drain of the second PMOS transistor and the groundvoltage and gates to the output of the decoder unit. In addition, thesecond NMOS transistor has a drain coupled to the drain of the secondPMOS transistor to generate the column selection signal.

[0034] The flash memory device further includes a column decoder fordividing the column selection transistors into predetermined stages. Thecolumn decoder includes first-stage column selection transistors forselecting at least two bitlines from among all the bitlines in responseto a group of the column selection signals and second-stage columnselection transistors for selecting a predetermined one of the bitlinesselected by the first-stage column selection transistors in response toanother group of the column selection signals in order to connect theselected bitline with a data line.

[0035] Another embodiment of the invention provides a stress test methodfor a flash memory device having column selection transistors thatselect a predetermined bitline among a plurality of bitlines coupled toflash memory cells. The stress test method includes activating all thecolumn selection signals, applying column selection signals coupled togates of the column selection transistors to a high voltage in responseto the activation of all the column selection signals, and decodinginputted column addresses in response to deactivation of all the columnselection signals in order to selectively turn on the column selectiontransistors. Preferably, the stress test is conducted for columnselection transistors with bitlines at a constant voltage level, e.g., aground voltage level.

[0036] While the specific embodiments described above may be susceptibleto various modifications and alternative forms, these embodiments weregiven only as examples and it should be understood that the invention isnot intended to be limited to the particular forms disclosed. Rather,the invention is to cover all modifications, equivalents, andalternatives falling within the spirit and scope of the invention asdefined by the following appended claims.

1. A flash memory device including a column predecoder, the columnpredecoder configured to control column selection transistors thatselect a predetermined bitline from among a plurality of bitlines thatare coupled to flash memory cells, the column predecoder comprising: abuffer unit configured to receive as input an all column selectionsignal; decoder units configured to decode an output of the buffer unitand a column address; and level shifters configured to generate columnselection signals that are applied to gates of the column selectiontransistors in response to an output of the decoder units, wherein thelevel shifters are configured to apply a high voltage to all the columnselection transistors during a stress test in response to the all columnselection signal.
 2. The flash memory device of claim 2, wherein thebuffer unit comprises an inverter.
 3. The flash memory device of claim1, wherein each of the decoder units comprise a NAND gate configured toreceive as input the output of the buffer unit and the column address.4. The flash memory device of claim 1, wherein the level shifterscomprise: first and second PMOS transistors each having a source, adrain, and a gate, wherein the sources of the first and second PMOStransistors are coupled to a high voltage and the gates thereof arecross-coupled to the drains thereof; an inverter configured to invertthe output of the decoder unit; a first NMOS transistor coupled betweenthe drain of the first PMOS transistor and a ground voltage, with a gatecoupled to an output of the inverter; and a second NMOS transistorcoupled between the drain of the second PMOS transistor and the groundvoltage, with a gate coupled to the output of the decoder unit, and witha drain coupled to the drain of the second PMOS transistor to generatethe column selection signal.
 5. The flash memory device of claim 1,further comprising a column decoder that divides the column selectiontransistors into predetermined stages, wherein the column decodercomprises: first-stage column selection transistors configured to selectat least two bitlines from among the plurality of bitlines in responseto a group of the column selection signals; and second-stage columnselection transistors configured to select a predetermined one of the atleast two bitlines in response to another group of the column selectionsignals and connect the predetermined one of the at least two bitlineswith a data line.
 6. The flash memory device of claim 5, wherein thecolumn selection transistors are NMOS transistors.
 7. The flash memorydevice of claim 1, wherein the high voltage is provided directly from anexternal source.
 8. The flash memory device of claim 1, wherein the highvoltage has a voltage level higher than a power supply voltage.
 9. Theflash memory device of claim 1, wherein a constant voltage level isapplied to the bitline during the stress test.
 10. The flash memorydevice of claim 9, wherein the constant voltage level is a groundvoltage level.
 11. A stress test method for a flash memory device havingcolumn selection transistors configured to select a predeterminedbitline from among a plurality of bitlines that are coupled to flashmemory cells, the stress test method comprising: activating a pluralityof column selection signals to a high voltage; applying the plurality ofcolumn selection signals to all the column selection transistors;deactivating all the column selection signals; turning on selected onesof the column selection transistors in response to deactivating all thecolumn selection signals by decoding a column address.
 12. The stresstest method of claim 11, wherein activating a plurality of columnselection signals to a high voltage comprises providing the high voltagedirectly from an external source.
 13. The stress test method of claim12, wherein providing the high voltage directly from an external sourcecomprises providing the high voltage with a voltage level higher than apower supply voltage.
 14. The stress test method of claim 11, furthercomprising applying a constant voltage to the plurality of bitlines. 15.The stress test method of claim 14, wherein applying a constant voltageto the plurality of bitlines comprises applying a ground voltage. 16.The stress test method of claim 11, wherein the column selectiontransistors are NMOS transistors.